Synthesis Based Design Techniques for Ultra Low Voltage Energy Efficient SoCs

Energy efficiency is increasingly becoming the main concern for many emerging system-on-chip (SoC) applications such as those for wireless sensor networks (WSNs) or portable electronics, which require ultra low power and high energy efficiency. Though voltage scaling down to near-(NVt) and subthreshold(sub-Vt) supply voltages has provided drastic quadratic savings in dynamic energy, design of circuits at ultra low voltages (ULVs) still poses important challenges, and methodologies in their current state still leave much space for optimization. For the circuits involved in SoCs, exponentially slower speeds in the ULV regime not only mean a limit on the throughput available, but also an increase in the significance of leakage current, which may undermine our purpose of energy efficiency. Increased sensitivity to process variation makes robust timing closure a key challenge at ULVs, which makes it exceptionally hard for industry to accept ULV designs as future solutions because of the low chip yield this entails. As to the SoC architecture, judicial considerations as to the size, amount, type, and communication of modules with respect to energy efficiency must be studied to ensure a deployable design. In this work, we first investigate the energy efficiency vs. module platform flexibility design space to answer the question how much energy efficiency is available in each type platform (general purpose processor, FPGA, or ASIC) in being the main driving force behind digital processing. Next, we explore if a body area sensor node SoC that uses several circuit and architectural methods and is capable of flexible bio-signal sampling and processing presses the point of minimal energy enough for battery-less operation. We delve into circuit design for ultra low power SoCs, and question the need for a new robust circuit topology to design standard cells for ULV, as well as questioning the need for a standard cell library characterization method that ensures robust operating logic cells. We ponder at whether a method for energy efficient and variation tolerant clock tree design for hold timing closure is needed, and if so what method we should use. And finally, we research to see if using latches in place of registers for both speed and energy optimization can lower the minimal energy point, change the analysis of optimal pipelining, and give light to an alternative approach to dynamic voltage and frequency scaling (DVFS). Our overall hypothesis is that the success of these projects will enable robust, energy efficient designs in the ULV region, and increase the recognition of ULV designs as viable solutions to industry related problems.